1. Field of the Invention:
The present invention relates to a transistor array device, and a method for producing the same. More particularly, the present invention relates to a thin film transistor array device adapted for use in large-screen active matrix display devices and a method for producing the same. Hereinafter, the thin film transistor will be referred to as "TFT".
2. Description of the Prior Art
Liquid crystal display devices which employ an active matrix system having a TFT array formed on an insulated substrate so as to drive picture element electrodes through the TFT are well known. The active matrix system has an advantage in that it can be applied to display devices designed to display on a large-scale screen with high density, whether the display is to be a reflecting type or a permeating type.
To obtain the TFT arrays, amorphous silicone (hereinafter referred to as "a-Si") or polycrystalline silicone is used as semiconductor material. FIG. 4 shows a conventional TFT array in which the rim of the layered portions is hatched with the central portion remaining unhatched for simplicity.
Referring to FIG. 5, the conventional fabrication of a TFT array device will be described:
Tantalum (Ta) is deposited on a glass substrate 21 by a spattering method to a thickness of 3,000 to 4,000 .ANG., and gate wirings 23 are formed in patterns by a photolithography or by an etching method. The gate wirings 23 can be formed by a lift-off method. A wider portion of the gate wiring 23 functions as a gate electrode 22. The surfaces of the gate electrode 22 and the gate wirings 23 are anodized so as to form an anodized film 24 which functions as a gate insulator film.
Subsequently, the anodized glass substrate 21 is covered with a gate insulating film 25, to the thickness of 2,000 to 4,000 .ANG. containing silicon nitride (hereinafter referred to as "SiNx") by a plasma activated chemical vapor deposition method (hereinafter referred to as plasma CVD method).
The gate insulator film 25 is covered with an a-Si(i) layer (150 to 1,000 .ANG. thick) and then with a SiNx layer (100 to 2,000 .ANG. thick). The a-Si layer later becomes a semiconductor layer 26, and the SiNx layer later becomes an insulator layer 27. Subsequently, the SiNx layer is formed in a desired pattern, and an insulator layer 27 is formed on a portion of the gate electrode 22 except for the outer part thereof.
The insulator layer 27 on the glass substrate 21 is covered with an a-Si(n.sup.+) layer (300 to 2,000 .ANG. thick) doped with phosphorus, which layer becomes a contact layer 28 by a plasma CVD. Finally, the a-Si(i) layer and the a-Si(n.sup.+) layer are formed in a desired pattern to form the semiconductor layer 26, and the contact layer 28 which is continuous on the insulator layer 27 at this stage.
A metal film of Mo, Ti, Al or the like is formed to the thickness of 2,000 to 10,000 .ANG. on the glass substrate 21 so as to cover the semiconductor layer 26 and the contact layer 28, and the metal film is formed in pattern by etching so that a source electrode 29, a source bus 30 and a drain electrode 31 are formed. In this way a TFT is formed. The contact layer 28 is also subjected to the etching on insulator layer 27, thereby separating into a first portion under the source electrode 29 and a second portion under the drain electrode 31. Finally, the source electrode 29, the source bus 30 and the drain electrode 31 are entirely covered with an indium tin oxide (ITO) film by spattering. The ITO film is formed in a desired pattern to form a picture element electrode 32.
Such TFTs are formed in plurality on the gate wiring 23 to form the TFT array. The source bus 30 is perpendicular to the extension of the gate wiring 23, and is connected to the respective source electrodes 29 of the TFTs.
In the active matrix display device employing the TFT arrays the scanning signals are consecutively input to the gate wiring 23, and picture element signals are input to the source bus 30 to drive the picture element electrode 32. The gate wiring 23 and the source bus 30 have 307,200 junctions in a display device having picture elements of 480.times.640. If leak occurs at one of these picture elements between the gate wiring 23 and the source bus 30, a cross-type line failure occurs. This line failure spoils the quality of the image, and reduces the efficiency of the display device.
In the known display device described above, Ta is used for the gate wiring 23 because of its capability of being coated with an anodized film 24 whereby the gate wiring 23 and the source bus 30 are insulated. When the gate wiring 23 is made of Ta, an advantage is that the gate wiring 23 has a smooth tapered side, which prevents the source bus 30 from breakage at its junctions.
On the other hand, a disadvantage is that in a large-scale display device having a long gate wiring 23, the scanning signals attenuate because of Ta having a large specific resistance. As a result, the brightness of picture elements are different between two points adjacent to the input section of the signals and remote from the input section, thereby resulting in the detrimental brightness gradient in picture elements spreading from the input section.
In order to solve such problems, one proposal shown in FIG. 6 is that the gate wiring has a dual layer structure, that is, an inner gate wiring 33 of metal having low specific resistance such as Al, Al-Si, or Al-Si-Cu, and an outer gate wiring 34 of the Ta. The advantage of this structure is that the inner gate wiring 33 avoids the undesired production of brightness gradient.
To prevent leaks from occurring at a junction by use of gate wirings 23 having the dual layer structure, it is essential to completely cover the inner gate wiring 33 with the outer gate wiring 34. This is because in the process of forming the outer gate wiring 34 of Ta in pattern by etching, the etching speed of Al and other metals is higher than the etching speed of Ta. However, the inner gate wiring 33 of Al, Al-Si, or Al-Si-Cu cannot be formed so as to have a smooth inclined side. The rough sides are likely to cause the outer gate wiring 34 overlaying the inner gate wiring 33 to break. If the outer gate wiring 34 is broken in this way, the coverage of the inner gate wiring 33 fails. In addition, in the process of removing the resist after the inner gate wiring 33 is formed, the inner gate wiring 33 is liable to hillocks and voids. If the killocks and voids occur on the inner gate wiring 33, its complete coverage becomes impossible. This causes leaks between the gate wiring 23 and the source bus 30 regardless of the existence of a gate insulating film 25.